
PROJ     := test_io
TOP_NAME := test_io


V_DIR := verilog/$(PROJ)

V_SRC := \
	$(V_DIR)/$(PROJ).v \
	verilog/core.v

OUT_VQM :=  	$(V_DIR)/$(PROJ).vqm
OUT_SRAM :=  	$(V_DIR)/$(PROJ)_sram.prg
OUT_AS := 		$(V_DIR)/$(PROJ)_master.bin
OUT_PS := 		$(V_DIR)/$(PROJ)_slave.bin

OUT_SRAM_TCL := fpga_sram.tcl
OUT_AS_TCL := fpga_as.tcl

AS_SCRIPT_CMD := -X "set DESIGN $(PROJ)" \
	-X "set TOP_MODULE $(TOP_NAME)"

# 这里的AS命令需要设置as.exe的目录
AS_CMD := af -B --batch --mode SYNPLICITY -X "set QUARTUS_SDC true" -X "set FITTING timing_more" -X "set FITTER hybrid" -X "set EFFORT highest" -X "set HOLDX default" -X "set SKEW basic" $(AS_SCRIPT_CMD)

$(OUT_VQM):$(V_SRC)
	yosys -p "read_verilog $(V_SRC)" -p "synth_intel -family cycloneive -top $(TOP_NAME) -iopads" -p "write_verilog -simple-lhs -attr2comment -defparam -nohex -renameprefix syn_ $@"

$(OUT_SRAM):$(OUT_VQM)
	cd verilog/$(PROJ)/ &&$(AS_CMD)
	echo "synthetical done"

$(OUT_AS):$(OUT_VQM)
	cd verilog/$(PROJ)/ &&$(AS_CMD)
	echo "synthetical done"

$(OUT_SRAM_TCL):$(OUT_SRAM)
	lua tools/prg_2ocdtcl.lua $(^) >$@

$(OUT_AS_TCL):$(OUT_AS) tools/asbin_2ocdtcl.lua
	lua tools/asbin_2ocdtcl.lua $(OUT_AS) >$@

all:$(OUT_AS_TCL)

clean:
	-rm $(OUT_SRAM_TCL) $(OUT_AS_TCL) $(OUT_PS) $(OUT_AS) $(OUT_VQM) $(OUT_SRAM) abc.history

build_sram:$(OUT_SRAM_TCL)
	echo "build done!"

build_as:$(OUT_AS_TCL)
	echo "build done!"

write_sram:$(OUT_SRAM_TCL)
	openocd -f link.cfg -f $<

write_as:$(OUT_AS_TCL)
	openocd -f link.cfg -f flash_read.tcl -f $< -c "exit"

write_mcu:
	make -f make_mcu.mk write_mcu

test_link:
	openocd -f link.cfg -f flash_read.tcl -c "exit"
	echo "read done!"
